Spring Semiconductor offers training programs with a strong focus on testability, using Siemen's Tessent Suite, a leading provider of solutions for chip design and test. Tessent EDA offers a comprehensive suite of tools that empower engineers to implement efficient and robust DFT practices.

Key Tessent EDA Solutions for DFT:

• Scan Chain Insertion and Management: Explore Tessent's offerings like Scan Design Architect (SDA) and TetraMAX for automated scan chain insertion, test pattern generation, and fault coverage analysis.
• Boundary Scan (BIST): Discuss Tessent tools like In-Situ Logic BIST (LBIST) and In-Situ Memory BIST (MBIST) that enable Built-In Self-Test capabilities within the design for efficient testing during manufacturing.
• Test Compression: Introduce Tessent's solutions like FastScan and Colossus that optimize test data volume for faster test execution times.
• Diagnosis and Yield Learning: Tessent's tools like Clarity and IronCat that assist engineers in analyzing test failures and improving yield during chip production.

1. Introduction to DFT

2. Mentor Tesscent EDA Solutions

3. BIST and Memories Solutions

4. JTAG and IO Test Solutions

5. DFT in SOC Applications